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ASAHI KASEI
[AKD4551]
AKD4551
Evaluation board Rev.C for AK4551
GENERAL DESCRIPTION AKD4551 is an evaluation board for the portable digital audio 20bit A/D and D/A converter, AK4551. The AKD4551 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). The A/D section can be evaluated by interfacing with AKM's DAC evaluation boards directly. The AKD4551 has the interface with AKM's wave generator using ROM data and AKM's ADC evaluation boards. Therefore, it's easy to evaluate the D/A section. The AKD4551 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. n Ordering guide
AKD4551 --Evaluation board for AK4551
FUNCTION * Compatible with 2 types of interface - Direct interface with AKM's A/D & D/A converter evaluation boards - DIT/DIR with optical input/output * BNC connector for an external clock input
2.2 3.6V
GND
CS8412 (DIR)
Opt In
AK4551
CS8402 (DIT)
Opt Out
A/D, D/A Data
Clock Generator
ROM Data
Figure 1. AKD4551 Block Diagram * Circuit diagram is attached at the end of this manual.
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ASAHI KASEI
[AKD4551]
n Input Circuit
External analog signal fed through the BNC connector is terminated by a resistor of 560 ohms. The resistor value should be properly selected in order to meet the output impedance of the signal source.
AINL(AINR) 560
4.7u +
470 AINL(AINR) 2.2n
Figure 2. Input buffer circuit on board * AKM assumes no responsibility for the trouble when using the circuit examples.
n Analog Output Circuit
The AK4551 includes a combination of switched-capacitor filter (SCF) and continuous-time filter (CTF), so any external filters are not required.
n Grounding and Power Supply Decoupling
To minimize the coupling by digital noise, VDD pin should be supplied from analog power supply in system. Decouling capacitors should be connected to AK4551 as near as possible. Especially, the capacitor between VDD and VSS pins should be connected nearest.
n Operation sequence
1) Set up the power supply lines. [VA] (orange) = 2.2 3.6V [VP] (orange) = 2.2 3.6V [VD] (red) = 3.6 5.0V [AGND] (black) = 0V [DGND] (black) = 0V : for VDD of AK4551 : for VP of 74HC4050 : for logic : for analog ground (including VSS of AK4551) : for logic ground
Each supply line should be distributed from the power supply unit. VP and VA must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4551 should be reset once bringing SW1,2 ( PWAD , PWDA ) "OFF" upon power-up.
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ASAHI KASEI
[AKD4551]
n Evaluation mode
Applicable Evaluation Mode 1) Evaluation of loopback mode (default) 2) Evaluation of D/A using ideal sin wave generated by ROM data 3) Evaluation of D/A using A/D converted data 4) Evaluation of D/A using DIR (Optical Link) 5) Evaluation of A/D using D/A converted data 6) Evaluation of A/D using DIT (Optical Link) 7) All interface signals including master clock are fed externally.
6) AKD43XX 5) D/A Board PORT2 DIT
AKD4551
1) PORT3 DIR
PORT1 10pin-Header CD Player 4) AKD53XX A/D Board 2) 3) ROM Board
1) Evaluation of loopback mode. (default) Nothing should be connected to PORT1/PORT3. In case of using external clock through a BNC connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE).This mode corresponds to only JP13 (X_SCLK) 64fs.
JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
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ASAHI KASEI
[AKD4551]
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data. Digital signals generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master clock is sent from AKD4551 to AKD43XX and SCLK, LRCK, SDTI are sent from AKD43XX to AKD4551. Nothing should be connected to PORT3. In case of using external clock through a BNC connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE). JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
3) Evaluation of D/A using A/D converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's A/D evaluation boards with PORT1. Nothing should be connected to PORT3. In case of using external clock through a BNC connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE). JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
4) Evaluation of D/A using DIR. (Optical link) PORT3 (TORX176) is used. DIR generates MCLK, SCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT1/PORT2. JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
5) Evaluation of A/D using D/A converted data. It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's D/A evaluation boards with PORT1. Nothing should be connected to PORT3. JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
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ASAHI KASEI
[AKD4551]
6) Evaluation of A/D using DIT. (Optical link) PORT2 (TOTX176) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier which equips DIR input. In case of using external clock through a BNC connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE). JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
7) All interfacing signals (MCLK, SCLK, LRCK) are fed from the external circuit through PORT1. Under the following set-up, all external signals needed for the AK4551 to operate could be fed through PORT1. In case of interfacing external sources to D/A converter, JP9 (SDTI) should be open. And in case of using A/D data to externally, JP9 (SDTI) is set ADC side. When JP9 (SDTI) is open, the A/D data can be output from the SDTO pin of PORT1 at the same time if JP7 (SDTO) is short. JP6 SCLK JP8 LRCK JP9 SDTI JP10 XTE JP12 XTI JP13 X_SCLK JP14 DIR
ADC
DIR
ADC
DIR
ADC
DIR EXT XTL DIR
32fs
64fs
ON
OFF
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ASAHI KASEI
[AKD4551]
n DIP switch set up
Upper-side is "ON" ("H") and lower-side is "OFF" ("L"). [SW3]: Sets the C-bit of CS8402. (Default is the consumer mode.) This set up does not affect the evaluation of the AK4551. In case of using DIT, need to set it up correctly. For more detailed configurations, please refer to the CS8402 data sheet. Switch 8 7, 6 OFF=0, ON=1 PRO = 0 C6 , C7 11 10 01 00 C9 1 0 C1 1 0 TRNPT 0 1 EM1, EM0 11 Contents
5
4
3
2, 1
Professional mode, C0=1 C6,C7 - Sampling frequency 00 - Not indicated. Receiver default to 48kHz. 01 - 48kHz 10 - 44.1kHz 11 - 32kHz C8,C9,C10,C11 - 1bit of channel mode 0000 - Mode not indicated. Receiver default to 2-channel mode. 0100 - Stereophonic. C1 - Audio mode 0 - Normal audio 1 - Non-audio Transparent mode *CS8402 is CRE Normal mode Transparent mode C2,C3,C4 - Encoded audio signal emphasis 000 - Emphasis not indicated. Receiver defaults to no emphasis with manual override enabled. 100 - None 10 110 - 50/15usec 01 111 - CCITT J.17 00 Table 1. DIP switch set-up of CS8402 (Professional mode) Contents
Switch 8 7 Default 6 Default 5 Default 4, 3
OFF=0, ON=1
Default 2, 1 Default
PRO = 1 Consumer mode, C0=1 C2 C2 - Copy 1 0 - Copy inhibited 0 1 - Copy permitted C3 C3,C4,C5 - Pre-emphasis 1 000 - None 0 100 - 50/15usec C15 C15 - General Status 1 0 - See the standard 0 1 - See the standard FC1,FC0 C24,C25,C26,C27 - Sampling frequency 0000 - 44.1kHz 00 0100 - 48kHz 01 1100 - 32kHz 10 0000 - 44.1kHz, CD mode 11 C8 , C9 C8-C14 - Category code 0000000 - General 11 0100000 - PCM encoder/decoder 10 1000000 - CD 01 1100000 - DAT 00 Table 2. DIP switch set-up of CS8402 (Consumer mode; default)
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ASAHI KASEI
[AKD4551]
n Other jumper pins set up
[JP1] (GND): Analog ground and digital ground open: separated AGND and DGND are connected near to AK4551 on the board. [JP2] (VP-VD): VP and VD open: separated short: common (The connector "VP" can be open.) [JP3, 4] (DEM0, DEM1): Set up the de-emphasis of AK4551 DEM1 (JP3) DEM0 (JP4) Mode open open 44.1kHz open short OFF short open 48kHz short short 32kHz Table 3. Set up the de-emphasis of AK4551 [JP5] (SCLK2): Phase of SCLK THR: SCLK is coincides with AK4551. INV: SCLK is inverted. [JP7] (SDTO): SDTO of AK4551 Always open. It is possible to short for evaluation mode 7. [JP11] (SPEED): Select of MCLK NORMAL: 256fs DOUBLE: 512fs
n The function of the toggle SW.
Upper-side is "ON" and lower-side is "OFF". [SW1] ( PWDA ): [SW2] ( PWAD ): [SW4] (DIT_RST): Resets the D/A of AK4551. Keep "ON" during normal operation. Resets the A/D of AK4551. Keep "ON" during normal operation. Resets the CS8402. "OFF" resets the internal counter of CS8402, then Bi-phase signal is not output. Keep "ON" during normal operation.
n Indication for LED
[LED1]: Indicate whether the input data of CS8412 is pre-emphasized or not. [LED2] (VERF): Monitor VERF pin of the CS8412. LED turns on when some error has occurred to CS8412.
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ASAHI KASEI
[AKD4551]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * SCLK * fs * Bit * Power Supply * Interface * Temperature 1. ADC VDD 2.5V Parameter S/(N+D) (-0.5dBFS) D-Range (-60dBFS) S/N (0 data) Measured Filter 20kHz LPF 20kLPF + A-weighted 20kLPF + A-weighted fs = 32kHz 84.3 dB 88.5 dB 88.5 dB fs = 44.1kHz 79.5 dB 89.3 dB 89.3 dB fs = 48kHz 79.5 dB 89.4 dB 89.4 dB
: Audio Precision, System two : 256fs : 64fs (ADC, DAC) : 32kHz, 44.1kHz, 48kHz : 20bit : VDD = VP = 2.5V, VD = 4.0V : DIT/DIR : Room
2. DAC VDD 2.5V Parameter S/(N+D) (0dBFS) D-Range (-60dBFS) S/N (0 data) Measured Filter 20kHz LPF 22kLPF + A-weighted 22kLPF + A-weighted fs = 32kHz 88.6 dB 92.5 dB 92.5 dB fs = 44.1kHz 87.9 dB 92.8 dB 93.0 dB fs = 48kHz 87.5 dB 92.9 dB 93.0 dB
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ASAHI KASEI
[AKD4551]
3. Graph (1) ADC
AKM
AK4551 ADC THD+N vs. Input Level V D D = 2 .5V, fs=44.1kHz, fin=1kHz
-70 -72 -74 -76
d B F S
-78 -80 -82 -84 -86 -88 -90 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
Fig 1. THD+N vs. Input Level
AKM
AK4551 ADC THD+N vs. Input Frequency V D D = 2 .5V, fs=44.1kHz, Input=-0.5dBr
-60 -65 -70 -75
d B F S
-80 -85 -90 -95 -100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 A D C L inearity V D D = 2 .5V, fs=44.1kHz, fin=1kHz
+0
-20
-40 d B F S
-60
-80
-100
-120 -120
-110
-100
-90
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Fig 3. Linearity
AKM
A K 4 5 5 1 A D C F requency Response V D D = 2 .5V, fs=44.1kHz, Input=-0.5dBr
+0 -0.2 -0.4 -0.6
d B F S
-0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 4. Frequency Response
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 A D C C rosstalk V D D = 2 .5V, fs=44.1kHz, Input=-0.5dBr
-50 -60 -70 -80
d B
-90 -100 -110 -120 -130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 5. Crosstalk
AKM
A K 4 5 5 1 A D C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=1kHz, Input=-0.5dBr
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 6. FFT Plot
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 A D C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=1kHz, Input=-60dBr
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 7. FFT Plot
AKM
A K 4 5 5 1 A D C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=None
+0 -20 -40 -60
d B F S
-80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 8. FFT Plot
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ASAHI KASEI
[AKD4551]
(2) DAC
AKM
AK4551 DAC THD+N vs. Input Level V D D = 2 .5V, fs=44.1kHz, fin=1kHz
-80 -82 -84 -86
d B r A
-88 -90 -92 -94 -96 -98 -100 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Fig 1. THD+N vs. Input Level
AKM
AK4551 DAC THD+N vs. Input Frequency V D D = 2 .5V, fs=44.1kHz, Input=0dBFS
-80 -82 -84 -86
d B r A
-88 -90 -92 -94 -96 -98 -100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 D A C L inearity V D D = 2 .5V, fs=44.1kHz, fin=1kHz
+0
-20
-40 d B r A -80
-60
-100
-120 -120
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Fig 3. Linearity
AKM
A K 4 5 5 1 D A C F requency Response V D D = 2 .5V, fs=44.1kHz, Input=0dBFS
+0.5 +0.4 +0.3 +0.2
d B r A
+0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Fig 4. Frequency Response
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 D A C C rosstalk V D D = 2 .5V, fs=44.1kHz, Input=0dBFS
-70
-80
-90
d B
-100
-110
-120
-130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 5. Crosstalk
AKM
A K 4 5 5 1 D A C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=1kHz, Input=0dBFS
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 6. FFT Plot
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ASAHI KASEI
[AKD4551]
AKM
A K 4 5 5 1 D A C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=1kHz, Input=-60dBFS
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 7. FFT Plot
AKM
A K 4 5 5 1 D A C F F T P lot V D D = 2 .5V, fs=44.1kHz, fin=None
+0 -20 -40
d B r A
-60 -80 -100 -120 -140 -160 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Fig 8. FFT Plot
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ASAHI KASEI
[AKD4551]
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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